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 FSEZ1216 -- Primary-Side-Regulation PWM Integrated Power MOSFET
September 2008
FSEZ1216 -- Primary-Side-Regulation PWM Integrated Power MOSFET
Features
Constant-Voltage (CV) and Constant-Current (CC) Control without Secondary-Feedback Circuitry Green-Mode Function: PWM Frequency Linearly Decreasing Fixed PWM Frequency at 42kHz with Frequency Hopping to Solve EMI Problem Cable Compensation in CV Mode Low Startup Current: 10A Low Operating Current: 3.5mA Peak-Current-Mode Control in CV Mode Cycle-by-Cycle Current Limiting VDD Over-Voltage Protection with Auto-Restart VDD Under-Voltage Lockout (UVLO) Fixed Over-Temperature Protection with Latch DIP-8 Package Available
Description
This highly integrated PWM controller, FSEZ1216, provides several features to enhance the performance of low-power flyback converters. The proprietary topology of FSEZ1216 enables simplified circuit design for battery charger applications. A low-cost, smaller, and lighter charger results when compared to a conventional design or a linear transformer. The startup current is only 10A, which allows use of large startup resistance for further power saving. To minimize the standby power consumption, the proprietary green-mode function provides off-time modulation to linearly decrease PWM frequency under light-load conditions. This green-mode function assists the power supply in meeting power conservation requirements. Using FSEZ1216, a charger can be implemented with few external components and minimized cost. A typical output CV/CC characteristic is shown in Figure 1. FSEZ1216 controller is available in an 8-pin DIP package.
Applications
Battery chargers for cellular phones, cordless phones, PDA, digital cameras, power tools Replaces linear transformer and RCC SMPS
Figure 1.
Typical Output V-I Characteristic
Ordering Information
Part Number
FSEZ1216NY
Operating Temperature Range
-40C to +105C
Eco Status
Green
Package
8-Lead, Dual Inline Package (DIP-8)
Packing Method
Tube
For Fairchild's definition of "green" Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
(c) 2008 Fairchild Semiconductor Corporation FSEZ1216 * Rev. 1.0.0
www.fairchildsemi.com
FSEZ1216 -- Primary-Side-Regulation PWM Integrated Power MOSFET
Application Diagram
Figure 2.
Typical Application
Internal Block Diagram
Brownout Protection
Vsah Vsah IPK
Figure 3.
(c) 2008 Fairchild Semiconductor Corporation FSEZ1216 * Rev. 1.0.0
Functional Block Diagram
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FSEZ1216 -- Primary-Side-Regulation PWM Integrated Power MOSFET
Marking Information
F- Fairchild logo Z- Plant Code X- 1 digit year code Y- 1 digit week code TT: 2 digits die run code T: Package type (N=DIP) P: Z: Pb free, Y: Green package M: Manufacture flow code
DXYTT ZXYTT EZ1216 TPM
Figure 4.
Top Mark
Pin Configuration
CS COMR COMI COMV
Figure 5.
DRAIN GND VDD VS
Pin Configuration
Pin Definitions
Pin #
1 2 3 4 5 6 7 8
Name
CS COMR COMI COMV VS VDD GND DRAIN
Description
Analog input, current sense. Connected to a current-sense resistor for peak-current-mode control in CV mode. The current-sense signal is also provided for output-current regulation in CC mode. Analog output, cable compensation. Connect a resistor between COMR and GND for cable loss compensation in CV mode. Analog output, current compensation. Output of the current error amplifier. Connect a capacitor between COMI pin and GND for frequency compensation. Analog output, voltage compensation. Output of the voltage error amplifier. Connect a capacitor between COMV pin and GND for frequency compensation. Analog input, voltage sense. Output-voltage-sense input for output-voltage regulation. Supply, power supply. Voltage reference, ground. Driver output, power MOSFET drain. This pin is the high-voltage power MOSFET drain.
(c) 2008 Fairchild Semiconductor Corporation FSEZ1216 * Rev. 1.0.0
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FSEZ1216 -- Primary-Side-Regulation PWM Integrated Power MOSFET
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Symbol
VVDD VVS VCS VCOMV VCOMI VDS ID IDM EAS IAR PD JA JC TJ TSTG TL ESD DC Supply Voltage
(1)
Parameter
VS Pin Input Voltage CS Pin Input Voltage Voltage Error Amplifier Output Voltage Voltage Error Amplifier Output Voltage Drain-Source Voltage Continuous Drain Current Pulsed Drain Current Single Pulse Avalanche Energy Avalanche Current Power Dissipation (TA50C) Thermal Resistance (Junction-to-Air) Thermal Resistance (Junction-to-Case) Operating Junction Temperature Storage Temperature Range Lead Temperature (Wave Soldering or IR, 10 seconds) Electrostatic Discharge Capability, Human Body Model, JEDEC: JESD22-A114 Electrostatic Discharge Capability, Charged Device Model, JEDEC: JESD22-C101 TC=25C TC=100C
Min.
-0.3 -0.3 -0.3 -0.3
Max.
30 7.0 7.0 7.0 7.0 600 1 0.6 4 33 1 800 113 67 +150
Unit
V V V V V V A A A mJ A mW C /W C /W C C C KV V
-55
+150 +260 2.5 1250
Note: 1. All voltage values, except differential voltages, are given with respect to GND pin.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA
Parameter
Operating Ambient Temperature
Conditions
Min.
-40
Typ.
Max.
+105
Unit
C
(c) 2008 Fairchild Semiconductor Corporation FSEZ1216 * Rev. 1.0.0
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FSEZ1216 -- Primary-Side-Regulation PWM Integrated Power MOSFET
Electrical Characteristics
VDD=15V and TA=25C unless otherwise specified.
Symbol VDD Section
VOP VDD-ON VDD-OFF IDD-ST IDD-OP IDD-GREEN VDD-OVP tD-VDDOVP
Parameter
Continuously Operating Voltage Turn-On Threshold Voltage Turn-Off Threshold Voltage Startup Current Operating Current Green Mode Operating Supply Current VDD Over-Voltage-Protection Level VDD Over-Voltage-Protection Debounce Time
Conditions
Min.
Typ.
Max.
25
Units
V V V A mA mA V s
15 4.5 0< VDD < VDD-ON-0.16V VDD=20V, fS=fOSC, VVS=2V, VCS=3V, CL=1nF VDD=20V, VVS=2.7V, fS=fOSC-N-MIN, VCS=0V, CL=1nF, VCOMV=0V VCS=3V, VVS=2.3V fs= fOSC, VVS=2.3V 27 100
16 5.0 10 3.5 1 28 250
17 5.5 20 5.0 2 29 400
Oscillator Section
Center Frequency fOSC tFHR fOSC-N-MIN fOSC-CM-MIN fDV fDT Frequency Frequency Hopping Range TA=25C TA=25C TA=25C VVS=2.7V, VCOMV=0V VVS=2.3V, VCS=0.5V VDD=10V to 25V TA=-40C to +85C 39 1.8 42 2.6 3 550 20 5 15 45 3.6 KHz ms Hz KHz % %
Frequency Hopping Period Minimum Frequency at No Load Minimum Frequency at CCM Frequency Variation vs. VDD Deviation Frequency Variation vs. Temperature Deviation
Voltage-Sense Section
IVS-UVP Itc VBIAS-COMV Sink Current for Brownout Protection IC Compensation Bias Current Adaptive Bias Voltage Dominated by VCOMV VCOMV=0V, TA=25C, RVS=20K RVS=20K 125 9.5 1.4 A A V
Current-Sense Section
tPD tMIN-N tMINCC DSAW VTH Propagation Delay to GATE Output Minimum On Time at No Load Minimum On Time in CC Mode Duty Cycle of SAW Limiter Threshold Voltage for Current Limit VVS=-0.8V, RS=2K, VCOMV=1V VVS=0V, VCOMV=2V 100 1100 400 40 1.3 200 ns ns ns % V
Continued on following page...
(c) 2008 Fairchild Semiconductor Corporation FSEZ1216 * Rev. 1.0.0
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FSEZ1216 -- Primary-Side-Regulation PWM Integrated Power MOSFET
Electrical Characteristics
VDD=15V and TA=25C unless otherwise specified.
Symbol
VVR VN VG IV-SINK IV-SOURCE VV-HGH VIR II-SINK II-SOURCE VI-HGH
Parameter
Reference Voltage
Conditions
Min.
2.475
Typ.
2.500 2.8 0.8 90 90
Max.
2.525
Units
V V V A A V
Voltage-Error-Amplifier Section
Green Mode Starting Voltage on fS=fOSC-2KHz, VVS=2.3V COMV Pin Green Mode Ending Voltage on COMV Pin Output Sink Current Output Source Current Output High Voltage Reference Voltage Output Sink Current Output Source Current Output High Voltage VCS=3V, VCOMI=2.5V VCS=0V, VCOMI=2.5V VCS=0V 4.5 fS=1KHz VVS=3V, VCOMV=2.5V VVS=2V, VCOMV=2.5V VVS=2.3V 4.5 2.475 2.500 55 55 2.525
Current-Error-Amplifier Section
V A A V
Cable Compensation Section
VCOMR Variation Test Voltage on COMR RCOMR=100k Pin for Cable Compensation Maximum Duty Cycle Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Maximum Continuous DrainSource Diode Forward Current Maximum Pulsed Drain-Source Diode Forward Current Static Drain-Source OnResistance Drain-Source Leakage Current Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance VGS=0V, VDS=25V, fS=1MHz
(2,3)
0.735
V
Internal MOSFET Section
DCYMAX BVDSS BVDSS /TJ IS ISM RDS(ON) IDSS tD-ON tr tD-OFF tf CISS COSS 75 ID=250A, VGS=0V ID=250A, Referenced to 25C 600 0.6 1 4 ID=0.5A, VGS=10V VDS=600V, VGS=0V, TC=25C VDS=480V, VGS=0V, TC=100C VDS=300V, ID=1.1A, RG=25 7 21 13 27 130 19 9.3 11.5 1 10 24 52 36 64 170 25 % V V/C A A A A ns ns ns ns pF pF
Over-Temperature-Protection Section
TOTP Threshold Temperature for (4) OTP +140 C
Notes: 2. Pulse test: pulse width 300s, duty cycle 2%. 3. Essentially independent of operating temperature. 4. When over-temperature protection is activated, the power system enters latch mode and output is disabled.
(c) 2008 Fairchild Semiconductor Corporation FSEZ1216 * Rev. 1.0.0 www.fairchildsemi.com 6
FSEZ1216 -- Primary-Side-Regulation PWM Integrated Power MOSFET
Typical Performance Characteristics
17
5.5
16.6
5.3
16.2
VDD-OFF (V)
-40 -30 -15 0 25 50 75 85 100 125
VDD-ON (V)
5.1
15.8
4.9
15.4
4.7
15
4.5 -40 -30 -15 0 25 50 75 85 100 125
Temperature (C)
Temperature (C)
Figure 6.
Turn-on Threshold Voltage (VDD-ON) vs. Temperature
Figure 7.
Turn-off Threshold Voltage (VDD-OFF) vs. Temperature
4.5
45 44 43 42 41 40 39 -40 -30 -15 0 25 50 75 85 100 125 -40 -30 -15 0 25 50 75 85 100 125
4.1
IDD-OP (mA)
3.7
3.3
2.9
2.5
Temperature (C)
fOSC (KHz)
Temperature (C)
Figure 8.
Operating Current (IDD-OP) vs. Temperature
Figure 9.
Center Frequency (fOSC) vs. Temperature
2.525
2.525
2.515
2.515
VVR (V)
2.495
VIR (V)
-40 -30 -15 0 25 50 75 85 100 125
2.505
2.505
2.495
2.485
2.485
2.475
2.475 -40 -30 -15 0 25 50 75 85 100 125
Temperature (C)
Temperature (C)
Figure 10. Reference Voltage (VVR) vs. Temperature
Figure 11. Reference Voltage (VIR) vs. Temperature
(c) 2008 Fairchild Semiconductor Corporation FSEZ1216 * Rev. 1.0.0
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FSEZ1216 -- Primary-Side-Regulation PWM Integrated Power MOSFET
Typical Performance Characteristics (Continued)
600 25
560
23
520
fOSC-CM-MIN (KHz)
-40 -30 -15 0 25 50 75 85 100 125
fOSC-N-MIN (Hz)
21
480
19
440
17
400
15 -40 -30 -15 0 25 50 75 85 100 125
Temperature (C)
Temperature (C)
Figure 12. Minimum Frequency at No Load (fOSC-N-MIN) vs. Temperature
Figure 13. Minimum Frequency at CCM (fOSC-CM-MIN) vs. Temperature
30 25
1000 950 900 850 800 750 700 -40 -30 -15 0 25 50 75 85 100 125 -40 -30 -15 0 25 50 75 85 100 125
SG (KHz/V)
15 10 5 0
Temperature (C)
tMIN-N (ns)
20
Temperature (C)
Figure 14. Green Mode Frequency Decreasing Rate (SG) vs. Temperature
Figure 15. Minimum On Time at No Load (tMIN-N) vs. Temperature
5
1
4
0.8
VN (V)
2
VG (V)
3
0.6
0.4
1
0.2
0 -40 -30 -15 0 25 50 75 85 100 125
0 -40 -30 -15 0 25 50 75 85 100 125
Temperature (C)
Temperature (C)
Figure 16. Green Mode Starting Voltage on COMV Pin (VN) vs. Temperature
Figure 17. Green Mode Ending Voltage on COMV Pin (VG) vs. Temperature
(c) 2008 Fairchild Semiconductor Corporation FSEZ1216 * Rev. 1.0.0
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FSEZ1216 -- Primary-Side-Regulation PWM Integrated Power MOSFET
Typical Performance Characteristics (Continued)
95 95
92
91
89
IV-SOURCE (A)
-40 -30 -15 0 25 50 75 85 100 125
IV-SINK (A)
87
86
83
83
79
80
75 -40 -30 -15 0 25 50 75 85 100 125
Temperature (C)
Temperature (C)
Figure 18. Output Sink Current (IV-SINK) vs. Temperature
Figure 19. Output Source Current (IV-SOURCE) vs. Temperature
65
65
62
62
59
II-SOURCE (A)
-40 -30 -15 0 25 50 75 85 100 125
II-SINK (A)
59
56
56
53
53
50
50 -40 -30 -15 0 25 50 75 85 100 125
Temperature (C)
Temperature (C)
Figure 20. Output Sink Current (II-SINK) vs. Temperature
Figure 21. Output Source Current (II-SOURCE) vs. Temperature
2
80
1.6
76
1.2
DCYMAX (%)
-40 -30 -15 0 25 50 75 85 100 125
VCOMR (V)
72
0.8
68
0.4
64
0
60 -40 -30 -15 0 25 50 75 85 100 125
Temperature (C)
Temperature (C)
Figure 22. Variation Test Voltage on COMR Pin for Cable Compensation (VCOMR) vs. Temperature
Figure 23. Maximum Duty Cycle (DCYMAX) vs. Temperature
(c) 2008 Fairchild Semiconductor Corporation FSEZ1216 * Rev. 1.0.0
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FSEZ1216 -- Primary-Side-Regulation PWM Integrated Power MOSFET
Functional Description
The proprietary topology of FSEZ1216 enables simplified circuit design for battery charger applications. Without secondary feedback circuitry, the CV and CC control can be achieved accurately. As shown in Figure 24, with the frequency-hopping and PWM operation, EMI problems can be solved by using minimized filter components. FSEZ1216 also provides many protection functions. The VDD pin is equipped with over-voltage protection, and under-voltage lockout. Pulse-by-pulse current limiting and CC control ensure over-current protection at heavy loads. The internal overtemperature-protection function shuts down the controller with latch when over heated. Figure 25. Green-Mode Operation (Frequency vs. VCOMV)
Constant Voltage (CV) and Constant Current (CC) Operation
An innovative technique of the FSEZ1216 can accurately achieve CV/CC characteristic output without secondary-side voltage or current-feedback circuitry. A feedback signal for CV/CC operation from the reflected voltage across the primary auxiliary winding is proportional to secondary winding, so provides controller the feedback signal from secondary side and achieves constant voltage output property. In constantcurrent output operation, this voltage signal is detected and examined by the precise constant current regulation controller, which then determines the on-time of the MOSFET to control input power and provides constant current output property. With feedback voltage VCS across current sense resistor, the controller can obtain input power of power supply. Therefore, the region of constant current output operation can be adjusted by current sense resistor.
Figure 24. Frequency Hopping
Startup Current
The startup current is only 10A, which allows a startup resistor with a high resistance and a low-wattage to supply the startup power for the controller. A 1.5M, 0.25W, startup resistor and a 10F/25V VDD hold-up capacitor are sufficient for an AC-to-DC power adapter with a wide input range (100VAC to 240VAC).
Operating Current
The operating current has been reduced to 3.5mA, which results in higher efficiency and reduces the VDD hold-up capacitance requirement. Once FSEZ1216 enter "deep" green mode, the operating current is reduced to 1.2mA, assisting the power supply in meeting the power conservation requirements.
Temperature Compensation
Built-in temperature compensation provides better constant voltage regulation at different ambient temperatures. This internal compensation current is a positive temperature coefficient (PTC) current that can compensate the forward-voltage drop of the secondary diode of varying with temperature. This variation caused output voltage to rise at high temperature.
Green-Mode Operation
Figure 25 shows the characteristics of the PWM frequency vs. the output voltage of the error amplifier (VCOMV). The FSEZ1216 uses the positive, proportional, output load parameter (VCOMV) as an indication of the output load for modulating the PWM frequency. In heavy load conditions, the PWM frequency is fixed at 42KHz. Once VCOMV is lower than VN, the PWM frequency starts to linearly decrease from 42KHz to 550Hz, providing further power savings and meeting international power conservation requirements.
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on spike occurs at the sense-resistor. To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. Conventional RC filtering can therefore be omitted. During this blanking period, the current-limit comparator is disabled and cannot switch off gate driver.
(c) 2008 Fairchild Semiconductor Corporation FSEZ1216 * Rev. 1.0.0
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FSEZ1216 -- Primary-Side-Regulation PWM Integrated Power MOSFET
Functional Description (Continued)
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds of the FSEZ1216 are fixed internally at 16V and 5V. During startup, the hold-up capacitor must be charged to 16V through the startup resistor to enable the FSEZ1216. The hold-up capacitor continues to supply VDD until power can be delivered from the auxiliary winding of the main transformer. VDD must not drop below 5V during startup. The UVLO hysteresis window ensures the hold-up capacitor is adequate to supply VDD during startup.
Gate Output
The BiCMOS output stage is a fast totem-pole gate driver. Cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 15V Zener diode to protect the internal power MOSFET transistors against undesired over-voltage gate signals.
Built-in Slope Compensation
The sensed voltage across the current-sense resistor is used for current-mode control and pulse-by-pulse current limiting. Built-in slope compensation improves stability and prevents sub-harmonic oscillations due to peak-current-mode control. A synchronized, positively sloped ramp is built-in at each switching cycle.
VDD Over-Voltage Protection (OVP)
VDD over-voltage protection prevents damage due to over-voltage conditions. When the VDD voltage exceeds 28V due to abnormal conditions, PWM pulses are disabled until the VDD voltage drops below the UVLO, then starts again. Over-voltage conditions are usually caused by open feedback loops.
Noise Immunity
Noise from the current sense or the control signal can cause significant pulse-width hopping, particularly in continuous-conduction mode. While slope compensation helps alleviate these problems, further precautions should still be taken. Good placement and layout practices should be followed. Avoiding long PCB traces and component leads, locating compensation and filter components near the FSEZ1216.
Over-Temperature Protection (OTP)
The FSEZ1216 has a built-in temperature sensing circuit to shut down PWM output once the junction temperature exceeds 140C. While PWM output is shut down, the VDD voltage gradually drops to the UVLO voltage. Some of the internal circuits are shut down and VDD gradually starts increasing again. When VDD reaches 16V, all the internal circuits, including the temperature-sensing circuit, start operating normally. If the junction temperature is still higher than 140C, the PWM controller shuts down immediately. This situation continues until the temperature drop below 110C.
(c) 2008 Fairchild Semiconductor Corporation FSEZ1216 * Rev. 1.0.0
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FSEZ1216 -- Primary-Side-Regulation PWM Integrated Power MOSFET
Applications Information
N1 1 R1 18 ohm /Wire Wound D1 1N4007 2 D2 1N4007 R3 CR22R N12 10 D5 2 N10 2 4 1 5A60 2
C1 N13 102P 1 N14 + C7 L2 5uH 220uF/10V 1 2 470uF/16V + C8 R8 510R/1206 2 N17 VO
L L1 2 1 2 1 N1
N3 R2 D4 1N4007 R4 750K +C3 10uF/400V N4 1 100K N7 1 D6 1N4007 N9 2 R6 CR270R 2 2 C5 4.7nF/1KV N6
1
TR 1
VO
P1
D3 1N4007
+ C2 1uF /400V
1
2
1
N N2
1
L4 1mH
P2 D7 FR103 3 EE16 8 AGND
2
R5 750K
AGND
1 2 C6 10uF/50V 1 +
U1 CS COMR COMI COMV 1 2 3 4 CS COMR COMI COMV FSEZ1216 DR AIN GND VDD VS 8 7 6 5 VDD VS
R7 137K
R14 C12 30K 47pF
C9 R12 1R3 R9 68K 1uF R10 200K
C10 68nF
R11 10nF
C11 56K
Figure 26. 5W (5V/1A) Application Circuit
BOM
Designator
D1, D2, D3, D4, D6 D5 D7 C1 C2 C3 C5 C6 C7 C8 C9 C10 C11 C12 R1 1N4007 SB560 FR103 1nF EC 1F/400V EC 10F/400V 4.7nF/1KV EC 10F/50V EC 470F/16V EC 220F/10 1F 68nF 10nF 47pF R 18
Part Type
R2 R3
Designator
R 100K R 22 R 750K R 270 R 137K R 510 R 68K R 200K R 56K R 1.3 R 30 5H 1mH
Part Type
R4, R5 R6 R7 R8 R9 R10 R11 R12 R14 L2 L4 T1 U1
EE16 (1.5mH) IC FSEZ1216
(c) 2008 Fairchild Semiconductor Corporation FSEZ1216 * Rev. 1.0.0
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FSEZ1216 -- Primary-Side-Regulation PWM Integrated Power MOSFET
Physical Dimensions
9.83 9.00
6.67 6.096
8.255 7.61
5.08 MAX
3.683 3.20
7.62
0.33 MIN (0.56) 2.54
3.60 3.00 0.56 0.355 1.65 1.27
7.62
0.356 0.20 9.957 7.87
NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-001 VARIATION BA B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994 E) DRAWING FILENAME AND REVSION: MKT-N08FREV2.
Figure 27. 8-Lead, Dual Inline Package (DIP-8)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/.
(c) 2008 Fairchild Semiconductor Corporation FSEZ1216 * Rev. 1.0.0 www.fairchildsemi.com 13
FSEZ1216 -- Primary-Side-Regulation PWM Integrated Power MOSFET
(c) 2008 Fairchild Semiconductor Corporation FSEZ1216 * Rev. 1.0.0
www.fairchildsemi.com 14


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